IS61VPD51218A
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Double cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for PBGA package
• Power Supply
LPD: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5%
VPD: Vdd 2.5V + 5%, Vddq 2.5V + 5%
• JEDEC 100-Pin TQFP,
119-pin PBGA and 165-pin PBGA package
• Lead-free available
DESCRIPTION
The ISSI IS61LPD/VPD25636A and IS61LPD/VPD51218A
are high-speed, low-power synchronous static
RAMs designed to provide burstable, high-performance
memory for communication and networking applications.
The IS61LPD/VPD25636A is organized as 262,144 words
by 36 bits, and the IS61LPD/VPD51218A is organized as
524,288 words by 18 bits. Fabricated with ISSI's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positiveedge-
triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte write
enable (BWE) input combined with one or more individual
byte write signals (BWx). In addition, Global Write (GW)
is available for writing all bytes at one time, regardless of
the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left
floating.
